Forum Discussion
Altera_Forum
Honored Contributor
8 years agoThanks Sstrell,
But I wonder why in another, quasi identical design, this annoying issue doesn't appear ? And in this design output clock isn't specified as false path.Thanks Sstrell,
But I wonder why in another, quasi identical design, this annoying issue doesn't appear ? And in this design output clock isn't specified as false path.