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Honored Contributor
Honored ContributorConstrained clock appears as unconstrained input
Hello, I've spent a considerable amount of time several months ago to look into timing constraint issues, but had never understood how it works ... all this staff, despite several manuals I loo...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- If a generated clock constraint targets an output pin, you will always see this. Perhaps there's some IP in this other design that handles it automatically for you. --- Quote End --- The both designs are very simple: top level wrapping Verilog module, where is instantiated Qsys module (the same Qsys in both).
