Honored ContributorHi folks, while I am familiar with set_input/output_delay -max where it specifies the maximum time taken for the data to travel to and from FPGA, I am still very confused with -min value. I noticed in most cases, we specify a negative value for -min but what does that actually mean? It will still take time to travel, just that the value should be smaller than -max but why the negative value?
Honored ContributorFor set_input_delay, which is using the Tco of the external device, I don't normally see negative numbers. For set_output_delay, you're spec'ing the input side of the external device, and ignoring baord delays it's basically:
set_output_delay -max $ext_device_tsu set_output_delay -min [expr -$ext_device_th] (The expr is just negating the hold of the external device). Basically the clock and data in the external device are racing to the FF. The data pin is usually right next to the register and short, while the clock path goes through some sort of clock tree and longer. So for hold we want the data path to be longer than the clock path and must hold it, but from a delay perspective we always look at it from data - clock, and since the clock is longer, it becomes a negative number. (FYI, I think Thold makes sense because we all learned that first, but it's not good for doing actual calculations, because it's really clock-data, where setup and everything else we do in path analysis is data-clock. SDC constraints are consistent that way, but it takes a while to get your head around because we've thought of Thold for so long. I just do the rule of thumb that if you have a hold spec, just invert it and then use it in SDC constraints as a delay) Also, I said set_input_delay is seldom negative. For a normal data coming out it's pretty much never negative, but for a source synchronous interface where the clock and data are coming out together, then it often is negative. In source-sync interfaces, the -max and -min values usually represent skew between data and clock, so if the skew could be +/-1ns, then your -max 1.0 and -min -1.0.Honored ContributorRyan, if you look at the TimeQuest User Guide from alterawiki that you published (Page 20), you can see that the set_input_delay -min has a -1.0 value (I believe this is non-source synchronous). So how do we relate this to the time taken from external device to reach the FPGA?
I am still quite confused on the mentioned data-clock statement. Shouldnt we be using the same data-clock/clock-data regardless of it is setup or hold analysis? Setup (max) is always easy and direct to understand but hold is always the confusing one. Do you have any other analogy on how to understand this?Honored ContributorIt's not normally negative, but with clock skew it's possible. I think I was trying to show a larger range between -max and -min, and wasn't thinking about how often a set_input_delay -min is actually negative.
I didn't explain the data-clock thing very well. I've actually written two different write-ups and realized they weren't going anywhere and probably not much different than what's in the User Guide. This can get difficult to talk about in the abstract and might be easier with what you're actually trying to do. Can you give an example of an interface you're trying to constrain, what you're trying to do and what you're confused on? I think that might be a better way to figure this out.Honored ContributorWithout referring to any specific example, can I say the delay value (min/max) simply dictates the time taken for the data to arrive at its latching register and hence there shouldnt be any negative value (non SS scenario) i.e - impossible for the data to travel before the source register launches it.
OR Based on the equation set_input_delay = Tcoext + Tdata - Clkskew --> There is a possiblity of negative value if Clkskew is very largeHonored ContributorYes, you're correct. Data_Delay - Clock_Skew, where Clock_Skew = (Latch_Clock_Delay - Launch_Clock_Delay). (Which you'll notice can be arranged to Launch_Clock_Delay + Data_Delay - Latch_Clock_Delay, which is how it's reported in TimeQuest Data Path, i.e. the Latch_Clock_Delay + Data_Delay are grouped together as Data Arrival Path, while Latch CLock Delay is Data Required.)
Your Data_Delay is always positive because of, well, physics. It's clock skew that can make it negative. Even in source synchronous interfaces, we're really skewing the latch clock so much that Latch_Clock_Delay = Launch_Clock_Delay + Data_Delay.Honored ContributorHonored ContributorThere are two other ways to handle clock delays/skew, either with an offset when defining the clock, or set_clock_latency. They behave differently, and usually I would choose set_clock_latency(I don't think offset has min/max variation, making it unuseful in most cases, but I'm not positive). But in the end, I never see anyone using either of these, and always see them rolling clock delays into the set_input/output_delay values. I've come to the conclusion it's easier that way, more common, etc. and have mainly gone that way myself. (Probably part of this comes from how Altera taught SDC constraints to FPGA designers who were unfamiliar with them, i.e. we didn't push set_clock_latency very much, but I also haven't seen it from ASIC designers who knew SDC better than anyone at Altera).
It's all just addition and subtraction though, so if you want to try and account for the clock with a different line item, or roll it into the external delay constraints, you get the same slack in the end.Honored ContributorThat means input_delay or iExt is simply = Data Arrival - Data Required, while setup slack = Data Required - Data Arrival. Can I then say iExt = - Setup Slack?
Honored ContributorSort of. I often write my IO constraints with the external delays at 0, just as a place holder. If, for example, my setup analysis then showed a slack of 3ns, I could put the external max delay at 3 and still meet timing. Of course, that's not really saying what the external delay is since there is no analysis on what's going on outside the FPGA. It's more saying, "do just as good as you did last time".
So yes, you could say it and probably pass timing, but it's not the real timing you need to meet, so I wouldn't recommend it.Honored Contributor
