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Altera_Forum
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9 years ago

Confused with set_input/output_delay command

Hi folks, while I am familiar with set_input/output_delay -max where it specifies the maximum time taken for the data to travel to and from FPGA, I am still very confused with -min value. I noticed i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Without referring to any specific example, can I say the delay value (min/max) simply dictates the time taken for the data to arrive at its latching register and hence there shouldnt be any negative value (non SS scenario) i.e - impossible for the data to travel before the source register launches it.

OR

Based on the equation set_input_delay = Tcoext + Tdata - Clkskew --> There is a possiblity of negative value if Clkskew is very large