Forum Discussion
Altera_Forum
Honored Contributor
10 years agoConfused with set_input/output_delay command
Hi folks, while I am familiar with set_input/output_delay -max where it specifies the maximum time taken for the data to travel to and from FPGA, I am still very confused with -min value. I noticed i...
Altera_Forum
Honored Contributor
10 years agoIt's not normally negative, but with clock skew it's possible. I think I was trying to show a larger range between -max and -min, and wasn't thinking about how often a set_input_delay -min is actually negative.
I didn't explain the data-clock thing very well. I've actually written two different write-ups and realized they weren't going anywhere and probably not much different than what's in the User Guide. This can get difficult to talk about in the abstract and might be easier with what you're actually trying to do. Can you give an example of an interface you're trying to constrain, what you're trying to do and what you're confused on? I think that might be a better way to figure this out.