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Altera_Forum
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9 years ago

Confused with set_input/output_delay command

Hi folks, while I am familiar with set_input/output_delay -max where it specifies the maximum time taken for the data to travel to and from FPGA, I am still very confused with -min value. I noticed i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Sort of. I often write my IO constraints with the external delays at 0, just as a place holder. If, for example, my setup analysis then showed a slack of 3ns, I could put the external max delay at 3 and still meet timing. Of course, that's not really saying what the external delay is since there is no analysis on what's going on outside the FPGA. It's more saying, "do just as good as you did last time".

So yes, you could say it and probably pass timing, but it's not the real timing you need to meet, so I wouldn't recommend it.