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Altera_Forum
Honored Contributor
10 years agoConfused with set_input/output_delay command
Hi folks, while I am familiar with set_input/output_delay -max where it specifies the maximum time taken for the data to travel to and from FPGA, I am still very confused with -min value. I noticed i...
Altera_Forum
Honored Contributor
10 years agoYes, you're correct. Data_Delay - Clock_Skew, where Clock_Skew = (Latch_Clock_Delay - Launch_Clock_Delay). (Which you'll notice can be arranged to Launch_Clock_Delay + Data_Delay - Latch_Clock_Delay, which is how it's reported in TimeQuest Data Path, i.e. the Latch_Clock_Delay + Data_Delay are grouped together as Data Arrival Path, while Latch CLock Delay is Data Required.)
Your Data_Delay is always positive because of, well, physics. It's clock skew that can make it negative. Even in source synchronous interfaces, we're really skewing the latch clock so much that Latch_Clock_Delay = Launch_Clock_Delay + Data_Delay.