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Without referring to any specific example, can I say the delay value (min/max) simply dictates the time taken for the data to arrive at its latching register and hence there shouldnt be any negative value (non SS scenario) i.e - impossible for the data to travel before the source register launches it.
OR
Based on the equation set_input_delay = Tcoext + Tdata - Clkskew --> There is a possiblity of negative value if Clkskew is very large
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set_input delay is defined by Synopsis as the offset of data from its launch edge at fpga pins. It does not mean board delay at all. Instead the board delay affects it as follows:
tco of external input device decides initial offset which is then modified by board:
if data and clock delay are equal then offset stays as tco till fpga pins
if data is late relative to clock then offset increases
if clock is delayed relative to data the offset decreases.
hence the formula of Tco + data delay - clock delay
It is unrealistic for such offset to be negative and even then you can move to nearby clock edge (wrap)
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