Confused with set_input/output_delay command

Ryan, if you look at the TimeQuest User Guide from alterawiki that you published (Page 20), you can see that the set_input_delay -min has a -1.0 value (I believe this is non-source synchronous). So how do we relate this to the time taken from external device to reach the FPGA?

I am still quite confused on the mentioned data-clock statement. Shouldnt we be using the same data-clock/clock-data regardless of it is setup or hold analysis? Setup (max) is always easy and direct to understand but hold is always the confusing one. Do you have any other analogy on how to understand this?