Confused with set_input/output_delay command

There are two other ways to handle clock delays/skew, either with an offset when defining the clock, or set_clock_latency. They behave differently, and usually I would choose set_clock_latency(I don't think offset has min/max variation, making it unuseful in most cases, but I'm not positive). But in the end, I never see anyone using either of these, and always see them rolling clock delays into the set_input/output_delay values. I've come to the conclusion it's easier that way, more common, etc. and have mainly gone that way myself. (Probably part of this comes from how Altera taught SDC constraints to FPGA designers who were unfamiliar with them, i.e. we didn't push set_clock_latency very much, but I also haven't seen it from ASIC designers who knew SDC better than anyone at Altera).

It's all just addition and subtraction though, so if you want to try and account for the clock with a different line item, or roll it into the external delay constraints, you get the same slack in the end.