Condition when in vhdl code

The values in when statements must be constants known at compile time.

So it won't work if i do this:

Case statements are for explicit constant values and need to cover all cases. If your want to use compare functions you must use an if statement.

how can i improve this to have less logical elements ?

Avoid using the elsif construct. It will create long logic chains that cannot execute in one clock cycle unless your clock is slow. You seem to have the same values assigned in multiple blocks. Try structuring it as as series of conditions for each variable separately. Remember, all of your logic will execute at the same time.

Indeed i have to simulate an electrocardiogram with 2 inputs (clk and hearts) and show the number of bpm with 8 leds (Very slow, slow, good1, good2,good3,good4, fast, very fast)

What fpga are you using, your code shouldn't use too many les. Can you pretty the code? Also, 60hz clock seems a little strange, how do you generate this clock? Usual and recommended method us to use the system clock with 60hz enable

I use the cpld 5M80ZE64C5. We had a lab at university and we had to do some experiment(like I said before with 2leds). Also our PCB has 2 clocks, from our datasheet we could see that we had one clock is 0.7 Hz to 48 and the other is 59 to 320 Hz. We had to choose the second clock and we took a small frequency(60). We had a work to do (with 8 leds) that use less than 22 LE and we have minus if we have more than 25. I link codes i tried and the first one for 2 leds (cardio.vhd)