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Altera_Forum
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9 years ago

Condition when in vhdl code

Sorry for my bad english, I have a problem in my code: i use the function case x is when y => but instead of a value i would like to have something (>= Y) i don't know if it's possible bu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

What fpga are you using, your code shouldn't use too many les. Can you pretty the code? Also, 60hz clock seems a little strange, how do you generate this clock? Usual and recommended method us to use the system clock with 60hz enable