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Altera_Forum
Honored Contributor
Honored ContributorCondition when in vhdl code
Sorry for my bad english, I have a problem in my code: i use the function case x is when y => but instead of a value i would like to have something (>= Y) i don't know if it's possible bu...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Avoid using the elsif construct. It will create long logic chains that cannot execute in one clock cycle unless your clock is slow. You seem to have the same values assigned in multiple blocks. Try structuring it as as series of conditions for each variable separately. Remember, all of your logic will execute at the same time. --- Quote End --- I would avoid the use of the word"execute". This implies software. A better phrase would be "logic that fails timing checks". But I do agree, you're better of separating the signals to have their own if sections. But other than that you can't really simplify it.
