Condition when in vhdl code

I use the cpld 5M80ZE64C5. We had a lab at university and we had to do some experiment(like I said before with 2leds). Also our PCB has 2 clocks, from our datasheet we could see that we had one clock is 0.7 Hz to 48 and the other is 59 to 320 Hz. We had to choose the second clock and we took a small frequency(60). We had a work to do (with 8 leds) that use less than 22 LE and we have minus if we have more than 25. I link codes i tried and the first one for 2 leds (cardio.vhd)