Condition when in vhdl code

how can i improve this to have less logical elements ?

if((cnt >= 80) and (cnt < 90)) then

leds_s <= "01";

leds_g <= "0000";

leds_f <= "00";

elsif(cnt >= 90) then

leds_s <= "11";

leds_g <= "0000";

leds_f <= "00";

elsif((cnt <= 18) and (cnt > 16)) then

leds_f <= "01";

leds_g <= "0000";

leds_s <= "00";

elsif(cnt <= 16) then

leds_f <= "11";

leds_g <= "0000";

leds_s <= "00";

elsif((cnt < 80) and (cnt >= 42)) then

leds_s <= "00";

leds_g <= "0001";

leds_f <= "00";

elsif((cnt < 42) and (cnt >= 29)) then

leds_s <= "00";

leds_g <= "0011";

leds_f <= "00";

elsif((cnt < 29) and (cnt >= 22)) then

leds_s <= "00";

leds_g <= "0111";

leds_f <= "00";

else

leds_s <= "11";

leds_g <= "1111";

leds_f <= "00";

end if;