Can I create VHDL-defined Dual-Port Dual-Clock ROMs with QuartusII 9.1 for Cyclone II

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The design is based on the "Dual-Port ROM" modified slightly with the "True Dual-Port RAM (dual-clock)" placed in "Insert Template->VHDL->Full Designs->RAMs and ROMs" path.

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Why? The NCO design should work fine with the original dual-port ROM template.

Without setting additional parameters, a true dual-clock RAM design will use double the RAM amount on Cyclone II to be compatible with revision A chips.

The reason I need to use Dual-Clock ROM is because of the speed. The main clock is 280MHz, which the memory won't pass the timing requirements (163MHz max), so the clock divided in half to make two 140MHz clocks, one inverted, to read the Dual-Port ROM. One port is read on positive clock and the other port on the inverted clock at 140MHz, effectively reading the ROM at 280MHz. Afterwards the two streams interleave to reassemble the single stream for the NCO output. The answer, a single clock is not sufficient.

It works fine, I have my own FM radio station (for about 20 meters), however it costs twice the ROM memory, as you said. Perhaps the cause is attributed to the additional parameters you mentioned (that I haven't set yet), the design of the ROM doesn't seem that complicated. If you can let me know where the information on where the additional parameters are, I will see if that solves the issue.

David K.

Two comments:

1. I don't see why you need dual clock. You can use a singe clock and delay one stream by a half clock cycle.

2. True dual port works with Cyclone II without doubling memory utilization if parameter CYCLONEII_SAFE_WRITE is set to VERIFIED_SAFE. Refer to the CII errata sheet for details.

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Two comments:

1. I don't see why you need dual clock. You can use a singe clock and delay one stream by a half clock cycle.

2. True dual port works with Cyclone II without doubling memory utilization if parameter CYCLONEII_SAFE_WRITE is set to VERIFIED_SAFE. Refer to the CII errata sheet for details.

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I don't see how delay of slow data(at 140) will work at required rate of 280. I think you can read a rom of double width getting two samples at a 140 rate then serialise it in the fast 280 domain.

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I don't see how delay of slow data(at 140) will work at required rate of 280.

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Use a simple (single clock) dual port ROM.

That's an interesting sugestion, I never thought of that one before. Remember that the delay function is also required for one of the address ports to sync with the 140MHz, since the address are sequentially generated with a 280MHz adder/counter.

However, the second reason I want to make a dual-clock ROM for the NCO is because I have to make serveral more NCO's for the processing path. My idea was to make a generic NCO which can be used by two seperate section , providing of course the WIDTH and LENGTH are the same, regardless of which clock or clock_enable used, to make the best use of memory space.

I checked out the Cyclone II Errata, and it claims ROM requires None for Quartus Action. Then I tried other Cyclone versions, and my NCO didn't optimize the memory, however using the ROM Dual-Port template with antother clock and another read process, and it DID perform the memory optimization!

There were a few things that cause it to creat double memory blocks...

-Using the WORD_T as an INTEGER rather than a STD_LOGIC_VECTOR.

-Using ROM : MEMORY_T as a CONSTANT rather than a SIGNAL.

-Adding a CLOCK_EN to either or both clocks.

Note, some of these affect single-clock as well.

The integer is convenient but the STD_LOGIC_VECTOR is pretty much the same data and (except for this exception) usually generates the same hardware PORT or SIGNAL.

I used a CONSTANT because a SIGNAL created 'Warning (10540): ... used explicit default value for signal "memory_data" because signal was never assigned a value', although using the correct design also removes the warning.

"Cyclone II M4K memory blocks support address clock enables,...", however I haven't been able to add a CLOCK_EN, or dual-clock with two of them, and maintain the memory optimization. Quite frequently, if possible, I use the same clock and use seperate clock enables for different timing, so effective I solved my initial question, however I have added the "...With CLOCK_ENABLES..." to my initial question.

Any Sugestions?

David K.