Can I create VHDL-defined Dual-Port Dual-Clock ROMs with QuartusII 9.1 for Cyclone II

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Two comments:

1. I don't see why you need dual clock. You can use a singe clock and delay one stream by a half clock cycle.

2. True dual port works with Cyclone II without doubling memory utilization if parameter CYCLONEII_SAFE_WRITE is set to VERIFIED_SAFE. Refer to the CII errata sheet for details.

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I don't see how delay of slow data(at 140) will work at required rate of 280. I think you can read a rom of double width getting two samples at a 140 rate then serialise it in the fast 280 domain.