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Altera_Forum
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11 years ago

Can I create VHDL-defined Dual-Port Dual-Clock ROMs with QuartusII 9.1 for Cyclone II

I have made an NCO which reads ROM memory. I have tried to make it a Dual-Port Dual-Clock ROM to be able to meet the timing, it works fine, however it is synthesized by duplicating the memory, 2 Sing...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Two comments:

1. I don't see why you need dual clock. You can use a singe clock and delay one stream by a half clock cycle.

2. True dual port works with Cyclone II without doubling memory utilization if parameter CYCLONEII_SAFE_WRITE is set to VERIFIED_SAFE. Refer to the CII errata sheet for details.