Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Can I create VHDL-defined Dual-Port Dual-Clock ROMs with QuartusII 9.1 for Cyclone II

I have made an NCO which reads ROM memory. I have tried to make it a Dual-Port Dual-Clock ROM to be able to meet the timing, it works fine, however it is synthesized by duplicating the memory, 2 Sing...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

--- Quote Start ---

The design is based on the "Dual-Port ROM" modified slightly with the "True Dual-Port RAM (dual-clock)" placed in "Insert Template->VHDL->Full Designs->RAMs and ROMs" path.

--- Quote End ---

Why? The NCO design should work fine with the original dual-port ROM template.

Without setting additional parameters, a true dual-clock RAM design will use double the RAM amount on Cyclone II to be compatible with revision A chips.