Honored Contributor
Honored ContributorThat's an interesting sugestion, I never thought of that one before. Remember that the delay function is also required for one of the address ports to sync with the 140MHz, since the address are sequentially generated with a 280MHz adder/counter.
However, the second reason I want to make a dual-clock ROM for the NCO is because I have to make serveral more NCO's for the processing path. My idea was to make a generic NCO which can be used by two seperate section , providing of course the WIDTH and LENGTH are the same, regardless of which clock or clock_enable used, to make the best use of memory space. I checked out the Cyclone II Errata, and it claims ROM requires None for Quartus Action. Then I tried other Cyclone versions, and my NCO didn't optimize the memory, however using the ROM Dual-Port template with antother clock and another read process, and it DID perform the memory optimization! There were a few things that cause it to creat double memory blocks... -Using the WORD_T as an INTEGER rather than a STD_LOGIC_VECTOR. -Using ROM : MEMORY_T as a CONSTANT rather than a SIGNAL. -Adding a CLOCK_EN to either or both clocks. Note, some of these affect single-clock as well. The integer is convenient but the STD_LOGIC_VECTOR is pretty much the same data and (except for this exception) usually generates the same hardware PORT or SIGNAL. I used a CONSTANT because a SIGNAL created 'Warning (10540): ... used explicit default value for signal "memory_data" because signal was never assigned a value', although using the correct design also removes the warning. "Cyclone II M4K memory blocks support address clock enables,...", however I haven't been able to add a CLOCK_EN, or dual-clock with two of them, and maintain the memory optimization. Quite frequently, if possible, I use the same clock and use seperate clock enables for different timing, so effective I solved my initial question, however I have added the "...With CLOCK_ENABLES..." to my initial question. Any Sugestions? David K.
