Can I create VHDL-defined Dual-Port Dual-Clock ROMs with QuartusII 9.1 for Cyclone II

The reason I need to use Dual-Clock ROM is because of the speed. The main clock is 280MHz, which the memory won't pass the timing requirements (163MHz max), so the clock divided in half to make two 140MHz clocks, one inverted, to read the Dual-Port ROM. One port is read on positive clock and the other port on the inverted clock at 140MHz, effectively reading the ROM at 280MHz. Afterwards the two streams interleave to reassemble the single stream for the NCO output. The answer, a single clock is not sufficient.

It works fine, I have my own FM radio station (for about 20 meters), however it costs twice the ROM memory, as you said. Perhaps the cause is attributed to the additional parameters you mentioned (that I haven't set yet), the design of the ROM doesn't seem that complicated. If you can let me know where the information on where the additional parameters are, I will see if that solves the issue.

David K.