Honored ContributorI'd like to understand. Suppose I do so
signal_1 <= signal_0;
signal_2 <= signal_1;
Honored ContributorHi,
It depends on where do you put those lines. 1. If you put this in clocked process like this process(reset_n, clk0)
begin
if reset_n='0' then
signal_1_synch <= '0';
signal_2_synch <= '0';
elsif (clk0'event and clk0 = '1') then
signal_1_synch <= signal_0_synch;
signal_2_synch <= signal_1_synch;
end if;
end process; signal_1 <= signal_0;
signal_2 <= signal_1;I see. Thank you.
One more question. Is it valid to do so?
process(reset_n, clk0)
begin
if reset_n='0' then
signal_1_synch <= '0';
signal_2_synch <= '0';
elsif (clk0'event and clk0 = '1') then
signal_1_synch <= signal_0_synch;
signal_2_synch <= signal_1_synch;
signal_0_synch <= '0';
end if;
end process;
process(reset_n, clk0)
begin
if reset_n='0' then
signal_1_synch <= '0';
signal_2_synch <= '0';
elsif (clk0'event and clk0 = '1') then
case cond is
when 1 => ------------
when 2 => signal_0_synch <= '1';
end case;
signal_1_synch <= signal_0_synch;
signal_2_synch <= signal_1_synch;
signal_0_synch <= '0';
end if;
end process;
That will not work. Your signal_0_synch will never be '1', because signal_0_synch will be assigned two times at same clock cycle (one in case statement and in last line). Try to explain what you are trying to do including more details.
Honored ContributorHonored ContributorA signal set under clock edge control (= a flip-flop) can be active for one clock period, but not shorter. Activation for one clock cycle can be e.g. achieved by sorting your code like this:
elsif (clk0'event and clk0 = '1') then
signal_0_synch <= '0';
case cond is
when 1 => ------------
when 2 => signal_0_synch <= '1';
end case;
signal_1_synch <= signal_0_synch;
signal_2_synch <= signal_1_synch;
end if; elsif (clk0'event and clk0 = '1') then
signal_0_synch <= '0';
case cond is
when 1 => ------------
when 2 => signal_0_synch <= '1';
end case;
signal_1_synch <= signal_0_synch;
signal_2_synch <= signal_1_synch;
end if;
