Buffering a signal.

Hi,

It depends on where do you put those lines.

1. If you put this in clocked process like this

 process(reset_n, clk0)
    begin
      if reset_n='0' then
         signal_1_synch  <= '0';
         signal_2_synch  <= '0';
      elsif (clk0'event and clk0 = '1') then
         signal_1_synch  <= signal_0_synch;
         signal_2_synch  <= signal_1_synch;
      end if;
    end process;

signal_2_synch will be 2 clock cyle delayed version of signal_0_synch.

2. If you write outside clocked proces like this

   signal_1 <= signal_0;
   signal_2 <= signal_1;

signal_2 would be same as signal_0.

Se image attached image:

https://www.alteraforum.com/forum/attachment.php?attachmentid=13296

So no it will not keep its value for two clock cycles.