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Altera_Forum
Honored Contributor
Honored ContributorBuffering a signal.
I'd like to understand. Suppose I do so
signal_1 <= signal_0;
signal_2 <= signal_1;
if signal_0 is '1' on the first clock and '0' on the second - does signal_2 keep its value for two clock...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I see. Thank you. One more question. Is it valid to do so? [snip] I need to reset signal_0_synch immediately and keep value of signal_2_synch for 2 clocks. --- Quote End --- It depends where signal_0_synch comes from. If this is the only process it is driven from then yes, assuming it does something else as otherwise it will always just be '0'. If it is driven elsewhere then no, its not valid as it's like connecting two wires together and you get multiple driver errors and unknowns in your simulation.
