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Altera_Forum
Honored Contributor
Honored ContributorBuffering a signal.
I'd like to understand. Suppose I do so
signal_1 <= signal_0;
signal_2 <= signal_1;
if signal_0 is '1' on the first clock and '0' on the second - does signal_2 keep its value for two clock...
Altera_ForumHonored Contributor
Honored ContributorThat will not work. Your signal_0_synch will never be '1', because signal_0_synch will be assigned two times at same clock cycle (one in case statement and in last line). Try to explain what you are trying to do including more details.
