Buffering a signal.

A signal set under clock edge control (= a flip-flop) can be active for one clock period, but not shorter. Activation for one clock cycle can be e.g. achieved by sorting your code like this:

      elsif (clk0'event and clk0 = '1') then
         signal_0_synch  <= '0';
         case cond is
               when 1 => ------------
               when 2 => signal_0_synch <= '1';
         end case;
         signal_1_synch  <= signal_0_synch;
         signal_2_synch  <= signal_1_synch;
      end if;

Consider that all registered signals are updated after all assignments scheduled at the respective clock edge have been made. If a signal is only assigned once, the assignment order in the sequential code doesn't matter. But if you have multiple assignments to the same signal in a process, the last assignment wins.