Forum Discussion
Altera_Forum
Honored Contributor
9 years agoBuffering a signal.
I'd like to understand. Suppose I do so
signal_1 <= signal_0;
signal_2 <= signal_1;
if signal_0 is '1' on the first clock and '0' on the second - does signal_2 keep its value for two clock...
Altera_Forum
Honored Contributor
9 years ago --- Quote Start --- It depends where signal_0_synch comes from. If this is the only process it is driven from then yes, assuming it does something else as otherwise it will always just be '0'. If it is driven elsewhere then no, its not valid as it's like connecting two wires together and you get multiple driver errors and unknowns in your simulation. --- Quote End --- I see. So it could be something like this?
process(reset_n, clk0)
begin
if reset_n='0' then
signal_1_synch <= '0';
signal_2_synch <= '0';
elsif (clk0'event and clk0 = '1') then
case cond is
when 1 => ------------
when 2 => signal_0_synch <= '1';
end case;
signal_1_synch <= signal_0_synch;
signal_2_synch <= signal_1_synch;
signal_0_synch <= '0';
end if;
end process;
This way I store the signal_0_synch and reset it. I need some buffer for another process to read the signal. If I reset it to quick It might be missed by other process.