Best power reduction approach when idle

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reset: is there a difference between synchronous and asynchronous reset?

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From your point of view they both keep the logic in a reset state. You may see a difference at the time of reset removal: with async reset you must be aware that not all involved registers will come out of reset at the same clock cycle and this could be a problem. So a sync reset is usually preferable.

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clock enable:not sure if stopping the clock enable signal will save any power :confused: the clock itself is still running...

settings the inputs to a constant, the same as clock enable...

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Any switching signal will consume power, so if you limit switching by stopping clocks you definitely spare power. Ideal CMOS-type logic draws no power when it stands still.

Remind that a major power consuption derives from output buffers driving external pins, so, if possibile, you can tristate them. Input signals are usually not a great concern, since power is borrowed from an external device.

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clock: if I stop the clock using a simple AND gate, will it affect timing? must I use a clock control block? (the entire design uses a single clock)

will it use another global clock network?

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Gating a clock is a bad practice and it is never recommended.

You'd better disable the PLL which generates it.

The safest option will be a clock enable. As Cris says, its switching logic that consumes power, so preventing a registers from changing will save some power.

Just one note to add to what cris said about resets: In Altera devices the registers do not have a sync reset input - when you infer registers from HDL if there is a sync reset, it actually muxes the input to the register with the reset and non-reset option. So if you want a true reset, you are best using an async reset template, with the async reset synchronised to the clock.

Cris, thanks for the detailed response.

as I wrote, my entire design uses a single clock , so stopping the PLL is not an option (other logic is still active)

Tricky, from what I understand from you, sync reset will takes extra LEs? linearly proportional to the number of signals with a reset value?

your recommendation, if I get you correctly, is an async reset, driven by an synced source(i.e. dff). this will solve the getting out of reset problem Cris wrote about.

I believe we reached the same conclusion in a different thread... for slightly different reasons. :)

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Tricky, from what I understand from you, sync reset will takes extra LEs? linearly proportional to the number of signals with a reset value?

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Yes an no. Most LEs wont have the all 4 (or 6 for newer devices) inputs used, so the sreset will just become another input to the LUT.

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as I wrote, my entire design uses a single clock , so stopping the PLL is not an option (other logic is still active)

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If you have a spare PLL, I suggest you replicate the clock net which needs to be disabled.

I think the active clock would lead to a reasonable power consuption even if you disable the related logic with reset or deasserting clock enable.

Infact, the clock network would still drive a lot of gates (although disabled), then a a big capacitance. This usually means a lot of current: roughly I = fCV

Cris, lets assume for portability and scalability sakes that I don't have a spare PLL.

what would you consider a lesser evil?