Best power reduction approach when idle

Cris, thanks for the detailed response.

as I wrote, my entire design uses a single clock , so stopping the PLL is not an option (other logic is still active)

Tricky, from what I understand from you, sync reset will takes extra LEs? linearly proportional to the number of signals with a reset value?

your recommendation, if I get you correctly, is an async reset, driven by an synced source(i.e. dff). this will solve the getting out of reset problem Cris wrote about.

I believe we reached the same conclusion in a different thread... for slightly different reasons. :)