Best power reduction approach when idle

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as I wrote, my entire design uses a single clock , so stopping the PLL is not an option (other logic is still active)

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If you have a spare PLL, I suggest you replicate the clock net which needs to be disabled.

I think the active clock would lead to a reasonable power consuption even if you disable the related logic with reset or deasserting clock enable.

Infact, the clock network would still drive a lot of gates (although disabled), then a a big capacitance. This usually means a lot of current: roughly I = fCV