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reset: is there a difference between synchronous and asynchronous reset?
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From your point of view they both keep the logic in a reset state. You may see a difference at the time of reset removal: with async reset you must be aware that not all involved registers will come out of reset at the same clock cycle and this could be a problem. So a sync reset is usually preferable.
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clock enable:not sure if stopping the clock enable signal will save any power :confused: the clock itself is still running...
settings the inputs to a constant, the same as clock enable...
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Any switching signal will consume power, so if you limit switching by stopping clocks you definitely spare power. Ideal CMOS-type logic draws no power when it stands still.
Remind that a major power consuption derives from output buffers driving external pins, so, if possibile, you can tristate them. Input signals are usually not a great concern, since power is borrowed from an external device.
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clock: if I stop the clock using a simple AND gate, will it affect timing? must I use a clock control block? (the entire design uses a single clock)
will it use another global clock network?
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Gating a clock is a bad practice and it is never recommended.
You'd better disable the PLL which generates it.
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