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Altera_Forum's avatar
Altera_Forum
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11 years ago

basic type conversion STD_LOGIC_VECTOR to INTEGER

Hi,

When I set up a new component under QSYS, under "Files" -> "Synthesis Files" I import my file delay_ctrl.vhd; when I run "Analyze Synthesis Files", I obtain the following message:

--- Quote Start ---

type of "writedata" does not agree with its usage as "integer" type

--- Quote End ---

I defined the input "writedata" as STD_LOGIC_VECTOR, but then later on I like to init an INTEGER by the content of writedata (which gives the actual error). If I define writedata already as INTEGER input signal, it won't be recongnized at all by QSYS, i.e. then does not show up in the "Signals" tab of "new component" in QSYS.

Questions: How to convert or add, respectively, a STD_LOGIC_VECTOR to an INTEGER? Or, which type to take correctly instead of STD_LOGIC_VECTOR? How to deal with this situation and what would be the best approach in my situation?

My code: 

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY delay_ctrl IS
PORT (
    clk : IN STD_LOGIC;
    pos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
    -- avalon interface inputs
    write : IN STD_LOGIC := '0';
-- FIXME: writedata does not appear in signals (QSYS)
    writedata : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000");
END delay_ctrl;
ARCHITECTURE delay_ctrl_arch OF delay_ctrl IS
(...)
SIGNAL tmp_delay: INTEGER := 0;
BEGIN
    clock_proc : PROCESS(clk)
    BEGIN
        IF rising_edge(clk) THEN
            -- get delay from HPS, is updated only in the NEXT round
            IF (write = '1') THEN
-- FIXME: writedata:STD_VECTOR_TYPE and tmp_delay:INTEGER are of different types
                tmp_delay <= tmp_delay + writedata;
            END IF;
(...)

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi,

    Since you are including the numeric_std library (which is the preferred library to use in any case) you need to go through a signal of type unsigned.

    I would use an intermediate signal defined as an unsigned, you can cast a std_logic_vector to unsigned by in this case:

    my_unsigned <= unsigned(writedata);

    This can then be followed by:

    tmp_delay <= tmp_delay + to_integer(my_unsigned);

    Or, you could do something like

    tmp_delay <= tmp_delay + to_integer(unsigned(writedata));

    Regards

    J
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    you need this line:

    tmp_delay <= tmp_delay + to_ingeger(unsigned(writedata));

    are you aaware though, that integers are 32 bits by default. To define their width in implementation, you need to give it a range when you declare it:

    signal tmp_delay : integer range 0 to 15; --will synthesise to 4 bits.

    Also, integers do not roll over. so when simulating, if you get to the end of the range of the integer, the simulator will throw an error. So you need to explicitly catch a roll-over case.

    To make your life easier in this situation, use an unsigned type instead:

    signal tmp_delay : unsigned(3 downto 0);

    tmp_delay <= tmp_delay + unsigned(writedata);

    This will roll over without a problem
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    you need this line:

    are you aaware though, that integers are 32 bits by default. To define their width in implementation, you need to give it a range when you declare it:

    signal tmp_delay : integer range 0 to 15; --will synthesise to 4 bits.

    Also, integers do not roll over. so when simulating, if you get to the end of the range of the integer, the simulator will throw an error. So you need to explicitly catch a roll-over case.

    --- Quote End ---

    Fair points!