basic type conversion STD_LOGIC_VECTOR to INTEGER

you need this line:

tmp_delay <= tmp_delay + to_ingeger(unsigned(writedata));

are you aaware though, that integers are 32 bits by default. To define their width in implementation, you need to give it a range when you declare it:

signal tmp_delay : integer range 0 to 15; --will synthesise to 4 bits.

Also, integers do not roll over. so when simulating, if you get to the end of the range of the integer, the simulator will throw an error. So you need to explicitly catch a roll-over case.

To make your life easier in this situation, use an unsigned type instead:

signal tmp_delay : unsigned(3 downto 0);

tmp_delay <= tmp_delay + unsigned(writedata);

This will roll over without a problem