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Altera_Forum's avatar
Altera_Forum
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11 years ago

basic type conversion STD_LOGIC_VECTOR to INTEGER

Hi, When I set up a new component under QSYS, under "Files" -> "Synthesis Files" I import my file delay_ctrl.vhd; when I run "Analyze Synthesis Files", I obtain the following message: ---...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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You can look at http://www.doulos.com/knowhow/vhdl_designers_guide/numeric_std/

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Thank you very much for the link!

Thank you all!!

The examples of type conversions helped me a lot, as also the very important hint, that there is no overrun protection in integer type.

Of course I was not aware of it. I really appreciate!!!