Basic setup in Quartus

You need to instantiate your Nios in the top.v for your new development board. I've done so as an example below.

module top
(
// {ALTERA_ARGS_BEGIN} DO NOT REMOVE THIS LINE!
    ADC_7,
    ADC_8,
    ADC_PSB1,
    ADC_PSB2,
    ADC_PSB3,
    ADC_PSB4,
    ADC_Vc1,
    ADC_Vc2,
    BP_SW_1,
    BP_SW_2,
    CLK50M,
    EXT_ADC1_CLK,
    EXT_ADC1_CS,
    EXT_ADC1_DATA,
    EXT_ADC2_CLK,
    EXT_ADC2_CS,
    EXT_ADC2_DATA,
    GD_FB,
    LED,
    LVDS_det,
    LVDS_RD_MINUS,
    LVDS_RD_PLUS,
    LVDS_TD_MINUS,
    LVDS_TD_PLUS,
    PSB_ENA,
    PSB_FAIL,
    PWM_S,
    RS232_CTS,
    RS232_RTS,
    RS232_RX,
    RS232_TX,
    SEL1,
    SEL2,
    SEL3,
    TEMP_CAP1,
    TEMP_CAP2,
    TEMP_PCB,
    TEMP_SW,
    xBP_SW_1,
    xBP_SW_2,
    xEXT_ADC1_CLK,
    xEXT_ADC1_CS,
    xEXT_ADC1_DATA,
    xEXT_ADC2_CLK,
    xEXT_ADC2_CS,
    xEXT_ADC2_DATA,
    xGD_FB,
    xPSB_ENA,
    xPSB_FAIL,
    xPWM_S,
    xTEMP_CAP1,
    xTEMP_CAP2,
    xTEMP_SW
// {ALTERA_ARGS_END} DO NOT REMOVE THIS LINE!
);
// {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
input            ADC_7;
input            ADC_8;
input            ADC_PSB1;
input            ADC_PSB2;
input            ADC_PSB3;
input            ADC_PSB4;
input            ADC_Vc1;
input            ADC_Vc2;
output           BP_SW_1;
output           BP_SW_2;
input            CLK50M;
output           EXT_ADC1_CLK;
output           EXT_ADC1_CS;
input            EXT_ADC1_DATA;
output           EXT_ADC2_CLK;
output           EXT_ADC2_CS;
input            EXT_ADC2_DATA;
input       GD_FB;
output      LED;
input            LVDS_det;
input            LVDS_RD_MINUS;
input            LVDS_RD_PLUS;
output           LVDS_TD_MINUS;
output           LVDS_TD_PLUS;
output           PSB_ENA;
input            PSB_FAIL;
output      PWM_S;
input            RS232_CTS;
output           RS232_RTS;
input            RS232_RX;
output           RS232_TX;
input            SEL1;
input            SEL2;
input            SEL3;
input            TEMP_CAP1;
input            TEMP_CAP2;
input            TEMP_PCB;
input       TEMP_SW;
output           xBP_SW_1;
output           xBP_SW_2;
output           xEXT_ADC1_CLK;
output           xEXT_ADC1_CS;
input            xEXT_ADC1_DATA;
output           xEXT_ADC2_CLK;
output           xEXT_ADC2_CS;
input            xEXT_ADC2_DATA;
input       xGD_FB;
output           xPSB_ENA;
input            xPSB_FAIL;
output      xPWM_S;
input            xTEMP_CAP1;
input            xTEMP_CAP2;
input       xTEMP_SW;
// {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
// {ALTERA_MODULE_BEGIN} DO NOT REMOVE THIS LINE!
// {ALTERA_MODULE_END} DO NOT REMOVE THIS LINE!
wire       nios_50M_clk;
wire       reset_n;
wire  LED_ctrl_from_nios;
wire  SW_to_nios;
assign nios_50M_clk = CLK50M;             // Local 50MHz osc on your new board means you don't need your 10MHz->50MHz PLL
assign reset_n = 1'b1;                    // Just tie reset_n high to take Nios out of reset from the start
assign LED = LED_ctrl_from_nios;     // Connect 3 LEDs to your control from your Nios
assign LED = 5'b0;                   // Tie off unused LEDs
assign SW_to_nios = {SEL3, SEL2, SEL1};   // A guess, assuming SEL1-3 are switches on your dev board. If not you will need to find some.
         // Instanciate your Nios module inside the outer 'top' wrapper module for your new dev board.
   nios_setup u0 (
      .clk_clk                               (nios_50M_clk),         //                            clk.clk
      .reset_reset_n                         (reset_n),              //                          reset.reset_n
      .led_io_external_connection_export     (LED_ctrl_from_nios),   //    led_pio_external_connection.export
      .sw_io_external_connection_export      (SW_to_nios),           // switch_pio_external_connection.export
            // Suspect you don't need the following two lines for your application. Either tie off (as below)
            //   or revisit in Qsys and modify your component to remove them.
      .modular_adc_0_adc_pll_clock_clk       (1'b0),                 //    modular_adc_0_adc_pll_clock.clk
      .modular_adc_0_adc_pll_locked_export   (1'b0)                  //   modular_adc_0_adc_pll_locked.export
    );
endmodule

Hi Alex thanks for the help...

hi could you show me the NIOS part in VHDL ? /thanks

Hi Alex

Yes, the auto-generated top level file can be used, but it's only a template containing all the I/O you've specified. It will not contain any design information.

Hi Alex

Hi Alex

--entity CellController is
	--port (
	--	clk_clk                             : in  std_logic                    := '0'; --                          clk.clk
	--	leds_external_connection_export     : out std_logic_vector(3 downto 0);        --     leds_external_connection.export
	--	modular_adc_0_adc_pll_clock_clk     : in  std_logic                    := '0'; --  modular_adc_0_adc_pll_clock.clk
	--	modular_adc_0_adc_pll_locked_export : in  std_logic                    := '0'; -- modular_adc_0_adc_pll_locked.export
	--	reset_reset_n                       : in  std_logic                    := '0'  --                        reset.reset_n
	--);
--end entity CellController;

-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other 
-- applicable license agreement, including, without limitation, 
-- that your use is for the sole purpose of programming logic 
-- devices manufactured by Altera and sold by Altera or its 
-- authorized distributors.  Please refer to the applicable 
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_syn_attributes.all;
entity top is
	port
	(
-- {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
		PSB_ENA : in std_logic;
		ADC_PSB1 : in std_logic;
		ADC_PSB2 : in std_logic;
		ADC_PSB3 : in std_logic;
		ADC_PSB4 : in std_logic;
		ADC_Vc1 : in std_logic;
		ADC_Vc2 : in std_logic;
		ADC_7 : in std_logic;
		ADC_8 : in std_logic;
		RS232_RX : in std_logic;
		RS232_CTS : in std_logic;
		EXT_ADC2_DATA : in std_logic;
		SEL1 : in std_logic;
		xEXT_ADC2_CS : in std_logic;
		xEXT_ADC2_CLK : in std_logic;
		xEXT_ADC1_CS : in std_logic;
		xBP_SW_2 : in std_logic;
		xBP_SW_1 : in std_logic;
		EXT_ADC1_CS : in std_logic;
		EXT_ADC1_CLK : in std_logic;
		xPSB_ENA : in std_logic;
		TEMP_CAP2 : in std_logic;
		TEMP_CAP1 : in std_logic;
		PSB_FAIL : in std_logic;
		SEL3 : in std_logic;
		EXT_ADC1_DATA : in std_logic;
		xPSB_FAIL : in std_logic;
		TEMP_PCB : in std_logic;
		SEL2 : in std_logic;
		RS232_TX : in std_logic;
		RS232_RTS : in std_logic;
		BP_SW_2 : in std_logic;
		BP_SW_1 : in std_logic;
		EXT_ADC2_CLK : in std_logic;
		EXT_ADC2_CS : in std_logic;
		xEXT_ADC2_DATA : in std_logic;
		xTEMP_CAP2 : in std_logic;
		xTEMP_CAP1 : in std_logic;
		xEXT_ADC1_DATA : in std_logic;
		nios_setup_clk_clk : in std_logic;
		nios_setup_led_io_external_connection_export : in std_logic_vector(7 downto 0);
		nios_setup_modular_adc_0_adc_pll_clock_clk : in std_logic;
		nios_setup_modular_adc_0_adc_pll_locked_export : in std_logic;
		nios_setup_reset_reset_n : in std_logic;
		alt_pll_areset : in std_logic;
		alt_pll_inclk0 : in std_logic;
		alt_pll_c0 : out std_logic;
		alt_pll_c1 : out std_logic;
		alt_pll_locked : out std_logic;
		LVDS_det : in std_logic;
		xEXT_ADC1_CLK : in std_logic;
		LVDS_RD : in std_logic;
		LVDS_TD : in std_logic;
		PWM_S : in std_logic_vector(0 to 3);
		GD_FB : in std_logic_vector(0 to 3);
		TEMP_SW : in std_logic_vector(0 to 3);
		xGD_FB : in std_logic_vector(0 to 3);
		xPWM_S : in std_logic_vector(0 to 3);
		xTEMP_SW : in std_logic_vector(0 to 3)
-- {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
	);
-- {ALTERA_ATTRIBUTE_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_ATTRIBUTE_END} DO NOT REMOVE THIS LINE!
end top;
architecture ppl_type of top is
-- {ALTERA_COMPONENTS_BEGIN} DO NOT REMOVE THIS LINE!
component alt_pll
	port
	(
		areset 	: in std_logic;
		inclk0 	: in std_logic;
		c0 		: out std_logic;
		c1 	 	: out std_logic;
		locked 	: out std_logic
	);
end component;
-- {ALTERA_COMPONENTS_END} DO NOT REMOVE THIS LINE!
begin
-- {ALTERA_INSTANTIATION_BEGIN} DO NOT REMOVE THIS LINE!
alt_pll_inst : alt_pll
	port map
	(
		areset => alt_pll_areset,
		inclk0 => alt_pll_inclk0,
		c0 	 => alt_pll_c0,
		c1 	 => alt_pll_c1,
		locked => alt_pll_locked
	);
-- {ALTERA_INSTANTIATION_END} DO NOT REMOVE THIS LINE!
end;	

Hi Alex just to let you know i think ive solved this part of the problem.

architecture ppl_type of top is
signal adc_10MHz_clk:	 	std_logic;
signal nios_50MHz_clk:	 	std_logic;
signal pll_locked:	 	std_logic;
signal reset_n:		 	std_logic;
component alt_pll
	port
	(
		areset 	: in std_logic;
		inclk0 	: in std_logic;
		c0 	: out std_logic;
		c1 	: out std_logic;
		locked 	: out std_logic
	);
end component;
component CellController
port
	(
		clk_clk                             : in  std_logic; --                          clk.clk
		leds_external_connection_export     : out std_logic_vector(3 downto 0); --     leds_external_connection.export
		modular_adc_0_adc_pll_clock_clk     : in  std_logic; --  modular_adc_0_adc_pll_clock.clk
		modular_adc_0_adc_pll_locked_export : in  std_logic; -- modular_adc_0_adc_pll_locked.export
		reset_reset_n                       : in  std_logic  --                        reset.reset_n
	);
end component;
begin
alt_pll_inst : alt_pll
	port map
	(
		areset => reset_in,
		inclk0 => clk_in_50MHz,
		c0 	 => adc_10MHz_clk,
		c1 	 => nios_50MHz_clk,
		locked => pll_locked
	);
	
CellController_inst : CellController
	port map
	(
			clk_clk                        => nios_50MHz_clk,
			leds_external_connection_export     => LED(3 downto 0),
			modular_adc_0_adc_pll_clock_clk     => adc_10MHz_clk,
			modular_adc_0_adc_pll_locked_export => pll_locked,
			reset_reset_n                       => reset_n	
	);
end;