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Altera_Forum
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11 years ago

Basic setup in Quartus

Hi i have demo project running on a eval board with a top.v file as entry. Now i have tried to make a new project to match a custom PCB but the generated top.v does look anything close to the othe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi Alex thanks for the help...

I was hoping the Pin Planner auto generated top level file could be used. I've specified both the PLL and the NiosII system in there as IP- components...But if they don't add them to the Top level file whats the point in that ?

/stefan