Basic setup in Quartus

Hi Alex

so i guess this vhdl taken from {My_custom}/syntesis/{My_custom.vhd}

--entity CellController is
	--port (
	--	clk_clk                             : in  std_logic                    := '0'; --                          clk.clk
	--	leds_external_connection_export     : out std_logic_vector(3 downto 0);        --     leds_external_connection.export
	--	modular_adc_0_adc_pll_clock_clk     : in  std_logic                    := '0'; --  modular_adc_0_adc_pll_clock.clk
	--	modular_adc_0_adc_pll_locked_export : in  std_logic                    := '0'; -- modular_adc_0_adc_pll_locked.export
	--	reset_reset_n                       : in  std_logic                    := '0'  --                        reset.reset_n
	--);
--end entity CellController;

needs to fit into auto generated top.vhd

-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other 
-- applicable license agreement, including, without limitation, 
-- that your use is for the sole purpose of programming logic 
-- devices manufactured by Altera and sold by Altera or its 
-- authorized distributors.  Please refer to the applicable 
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_syn_attributes.all;
entity top is
	port
	(
-- {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
		PSB_ENA : in std_logic;
		ADC_PSB1 : in std_logic;
		ADC_PSB2 : in std_logic;
		ADC_PSB3 : in std_logic;
		ADC_PSB4 : in std_logic;
		ADC_Vc1 : in std_logic;
		ADC_Vc2 : in std_logic;
		ADC_7 : in std_logic;
		ADC_8 : in std_logic;
		RS232_RX : in std_logic;
		RS232_CTS : in std_logic;
		EXT_ADC2_DATA : in std_logic;
		SEL1 : in std_logic;
		xEXT_ADC2_CS : in std_logic;
		xEXT_ADC2_CLK : in std_logic;
		xEXT_ADC1_CS : in std_logic;
		xBP_SW_2 : in std_logic;
		xBP_SW_1 : in std_logic;
		EXT_ADC1_CS : in std_logic;
		EXT_ADC1_CLK : in std_logic;
		xPSB_ENA : in std_logic;
		TEMP_CAP2 : in std_logic;
		TEMP_CAP1 : in std_logic;
		PSB_FAIL : in std_logic;
		SEL3 : in std_logic;
		EXT_ADC1_DATA : in std_logic;
		xPSB_FAIL : in std_logic;
		TEMP_PCB : in std_logic;
		SEL2 : in std_logic;
		RS232_TX : in std_logic;
		RS232_RTS : in std_logic;
		BP_SW_2 : in std_logic;
		BP_SW_1 : in std_logic;
		EXT_ADC2_CLK : in std_logic;
		EXT_ADC2_CS : in std_logic;
		xEXT_ADC2_DATA : in std_logic;
		xTEMP_CAP2 : in std_logic;
		xTEMP_CAP1 : in std_logic;
		xEXT_ADC1_DATA : in std_logic;
		nios_setup_clk_clk : in std_logic;
		nios_setup_led_io_external_connection_export : in std_logic_vector(7 downto 0);
		nios_setup_modular_adc_0_adc_pll_clock_clk : in std_logic;
		nios_setup_modular_adc_0_adc_pll_locked_export : in std_logic;
		nios_setup_reset_reset_n : in std_logic;
		alt_pll_areset : in std_logic;
		alt_pll_inclk0 : in std_logic;
		alt_pll_c0 : out std_logic;
		alt_pll_c1 : out std_logic;
		alt_pll_locked : out std_logic;
		LVDS_det : in std_logic;
		xEXT_ADC1_CLK : in std_logic;
		LVDS_RD : in std_logic;
		LVDS_TD : in std_logic;
		PWM_S : in std_logic_vector(0 to 3);
		GD_FB : in std_logic_vector(0 to 3);
		TEMP_SW : in std_logic_vector(0 to 3);
		xGD_FB : in std_logic_vector(0 to 3);
		xPWM_S : in std_logic_vector(0 to 3);
		xTEMP_SW : in std_logic_vector(0 to 3)
-- {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
	);
-- {ALTERA_ATTRIBUTE_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_ATTRIBUTE_END} DO NOT REMOVE THIS LINE!
end top;
architecture ppl_type of top is
-- {ALTERA_COMPONENTS_BEGIN} DO NOT REMOVE THIS LINE!
component alt_pll
	port
	(
		areset 	: in std_logic;
		inclk0 	: in std_logic;
		c0 		: out std_logic;
		c1 	 	: out std_logic;
		locked 	: out std_logic
	);
end component;
-- {ALTERA_COMPONENTS_END} DO NOT REMOVE THIS LINE!
begin
-- {ALTERA_INSTANTIATION_BEGIN} DO NOT REMOVE THIS LINE!
alt_pll_inst : alt_pll
	port map
	(
		areset => alt_pll_areset,
		inclk0 => alt_pll_inclk0,
		c0 	 => alt_pll_c0,
		c1 	 => alt_pll_c1,
		locked => alt_pll_locked
	);
-- {ALTERA_INSTANTIATION_END} DO NOT REMOVE THIS LINE!
end;	

im not sure how the clock should be mapped, as of now i mapped nios_setup_clk_clk to (IO_bank2, pin 27)in the pin planner but i should also be mapped to the PLL.

ive added a PLL IP-component in the Quartus project and in the Pin-planner but not in Qsys, hope this is correct.

thanks in advance...

/stefan