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Altera_Forum
Honored Contributor
Honored ContributorBasic setup in Quartus
Hi i have demo project running on a eval board with a top.v file as entry. Now i have tried to make a new project to match a custom PCB but the generated top.v does look anything close to the othe...
Altera_ForumHonored Contributor
Honored ContributorHi Alex
Just been reading on the "Altera Modular ADC core" IP found in Qsys the ADC runs at 1MHz and clock must be a factor of 2,10,20,40 or 80, so why would i go without the PLL to generate the 10MHz clock ? /stefan
