Honored Contributor
Honored ContributorYes, the auto-generated top level file can be used, but it's only a template containing all the I/O you've specified. It will not contain any design information.
You mention you have a Qsys project for both projects. So, when you generated that for your custom board, that will create a '{my_design}.v' file in a '{my_design}/synthesis' sub-directory in your project folder (where '{my_design}' matches the name of your Qsys '{my_design}.qsys' project file in your project directory). You need to instantiate that into your 'top.v' file that the Pin Planner generated for you. That's more or less what I did for you before but I had to guess a little based on the info you posted. Yes, you'll need a 10MHz clock for the ADC. So, if your custom board has a 50MHz clock source you're going to have to generate the 10MHz - I recommend using a PLL. --- Quote Start --- could you show me the NIOS part in VHDL... --- Quote End --- Everything you've posted has been Verilog. I suggest you stick with one HDL for the time being. If you're still struggling attach the '{my_design}.v' file to this post and I'll have a look in conjunction with the 'top.v' I/O wrapper file that you posted previously. Cheers, Alex