Basic setup in Quartus

Hi Alex just to let you know i think ive solved this part of the problem.

architecture ppl_type of top is
signal adc_10MHz_clk:	 	std_logic;
signal nios_50MHz_clk:	 	std_logic;
signal pll_locked:	 	std_logic;
signal reset_n:		 	std_logic;
component alt_pll
	port
	(
		areset 	: in std_logic;
		inclk0 	: in std_logic;
		c0 	: out std_logic;
		c1 	: out std_logic;
		locked 	: out std_logic
	);
end component;
component CellController
port
	(
		clk_clk                             : in  std_logic; --                          clk.clk
		leds_external_connection_export     : out std_logic_vector(3 downto 0); --     leds_external_connection.export
		modular_adc_0_adc_pll_clock_clk     : in  std_logic; --  modular_adc_0_adc_pll_clock.clk
		modular_adc_0_adc_pll_locked_export : in  std_logic; -- modular_adc_0_adc_pll_locked.export
		reset_reset_n                       : in  std_logic  --                        reset.reset_n
	);
end component;
begin
alt_pll_inst : alt_pll
	port map
	(
		areset => reset_in,
		inclk0 => clk_in_50MHz,
		c0 	 => adc_10MHz_clk,
		c1 	 => nios_50MHz_clk,
		locked => pll_locked
	);
	
CellController_inst : CellController
	port map
	(
			clk_clk                        => nios_50MHz_clk,
			leds_external_connection_export     => LED(3 downto 0),
			modular_adc_0_adc_pll_clock_clk     => adc_10MHz_clk,
			modular_adc_0_adc_pll_locked_export => pll_locked,
			reset_reset_n                       => reset_n	
	);
end;