Altera_Forum
Honored Contributor
17 years agoAlternative to weak pull-up for I/O during configuration?
Hello,
I've got the following problem: I use a Cyclone II FPGA in a complex design. Some User I/Os are connected to npn transistors. The problem is, that during configuration thru an epcs4 device the outputs are weak pull-up. This means, that the npn transistors connected to these outputs are conductive during configuration (circa 260ms). The Design works properly on a ready developed PCB, but the Quality Management in my Company does not allow these transistors to be conductive during power-up. It is also not possible to add some pull-down resistors, because the PCB design should not be changed. Is there any possibility to pull-down the USER I/O Pins during configuration? Maybe a little tick in Quartus settings? I hope somenone knows what I mean and has a solution! Thanks in advance Stefan PS: Sorry for my bad english!