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Altera_Forum
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17 years ago

Alternative to weak pull-up for I/O during configuration?

Hello, I've got the following problem: I use a Cyclone II FPGA in a complex design. Some User I/Os are connected to npn transistors. The problem is, that during configuration thru an epc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I seriously care about it, cause I have hardware connected to some I/O pins that may be instantly damaged when receiving illegal signal patterns.