Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Alternative to weak pull-up for I/O during configuration?

Hello, I've got the following problem: I use a Cyclone II FPGA in a complex design. Some User I/Os are connected to npn transistors. The problem is, that during configuration thru an epc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

--- Quote Start ---

I seriously care about it, cause I have hardware connected to some I/O pins that may be instantly damaged when receiving illegal signal patterns.

--- Quote End ---

I see. You are using the weak pull-ups, not for the purpose of avoiding floating inputs on the FPGA, but also for providing a defined power-up output level.

I assumed that in those applications where the power-up level is critical, an external pull-up or pull-down would be used, but I guess I was wrong.