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Altera_Forum
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17 years ago

Alternative to weak pull-up for I/O during configuration?

Hello, I've got the following problem: I use a Cyclone II FPGA in a complex design. Some User I/Os are connected to npn transistors. The problem is, that during configuration thru an epc...
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Altera_Forum
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17 years ago

Hi FvM,

Thanks for your reply!

I've expected that there´s no way to change the USER I/O behaviour during configuration! I think I have to make a redesign of the PCB to achieve the behaviour I need. Unfortunately it´s not possible to solder some additional pull-down resistors on the PCB, because the transistors are in a SOT 363 Package. Maybe it´s possible to add some external inverters on the pcb and change the vhdl file to change the behaviour.