We are not getting proper data when we do a read access to the on-chip memory via the AXI interface.

Hi, Our hardware controller has AXI Master interface, hence we are using the AXI bridge to connect to the Avalon interface of the on-chip memory. Do you see any issue with this? Rgds, sunil

Hi, Our controller has both AHB slave as well as AXI Master interface. So the bridge component that we created in the QSYS system has both AHB and AXI interfaces. AHB interface is used to access our Controller’s internal registers from NIOS II processor. AXI interface is used to access the on-chip memory from our controller AHB interface works fine, we are able to read/write to our Controller’s internal registers from NIOS II processor. The issue is seen with AXI interface, when we do a read access to on-chip memory from our controller, we are not getting back the data properly. So removing the bridge will not help in our testing. Do you have any other suggestion on how to connect the AXI interface form our controller to the Avalon interface of the on-chip memory? Rgds, sunil

Hi, Our controller is a huge design with hundreds of modules. How to put it inside the Qsys design? Could you pl. give us some idea? Rgds, sunil

Hi, Thanks, will go through the youtube video. But to connect NIOS II CPU & On-chip memory with our standalone controller design, we created one bridge component in QSYS. Pl. refer to the attached diagram. Will this not work? Rgds, sunil

Hi, I went through both the youtube videos. As per the first video only, we had created a bridge component and instantiated in the QSYS design. The second video talks about the interconnect components being used. I did check the same in our design, could see various components being used to convert from Avalon to AHB as well as Avalon to AXI interfaces. I’m not sure what to check exactly in this as I am not familiar with these interconnect components. Is there anything specific I need to check? Rgds, sunil