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SKuma36's avatar
SKuma36
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

We are not getting proper data when we do a read access to the on-chip memory via the AXI interface.

Hi, We are using Arria10 FPGA to implement our custom IP controller. The controller has both AHB slave as well as AXI master interfaces. The controller's registers are accessed using NIOS II Process...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
7 years ago

The bridge that you are using uses AHB, which means there are 3 conversion happening avalon -> AHB -> axi

Are you sure you using the correct bridge?

As mention, can you remove the bridge temporally to make the test so that we can Isolate those issue are comming out from the bridge.