We are not getting proper data when we do a read access to the on-chip memory via the AXI interface.

Hi, I went through both the youtube videos. As per the first video only, we had created a bridge component and instantiated in the QSYS design. The second video talks about the interconnect components being used. I did check the same in our design, could see various components being used to convert from Avalon to AHB as well as Avalon to AXI interfaces. I’m not sure what to check exactly in this as I am not familiar with these interconnect components. Is there anything specific I need to check? Rgds, sunil