Forum Discussion
SKuma36
Occasional Contributor
Occasional ContributorWe are not getting proper data when we do a read access to the on-chip memory via the AXI interface.
Hi, We are using Arria10 FPGA to implement our custom IP controller. The controller has both AHB slave as well as AXI master interfaces. The controller's registers are accessed using NIOS II Process...
KennyT_altera
Super Contributor
Super ContributorI can see that your axi slave is exported out from the qsys. Which means your controller is a standalone design? Can you try to make your controller to put in the qsys design?
