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SKuma36's avatar
SKuma36
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

We are not getting proper data when we do a read access to the on-chip memory via the AXI interface.

Hi, We are using Arria10 FPGA to implement our custom IP controller. The controller has both AHB slave as well as AXI master interfaces. The controller's registers are accessed using NIOS II Process...
SKuma36's avatar
SKuma36
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
Hi, Thanks, will go through the youtube video. But to connect NIOS II CPU & On-chip memory with our standalone controller design, we created one bridge component in QSYS. Pl. refer to the attached diagram. Will this not work? Rgds, sunil