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Altera_Forum's avatar
Altera_Forum
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19 years ago

SDRam Controller is there a better one ?

Maybe somebody has a recomendation for me ...

I use the sdram controller that is part of the sopc builder.

The external sdram is 2 chips each 16 bit wide.

Inside the FPGA cycloneII there are several avalon masters.

NiosII, 100MBit Ethernet MAC and some custom avalon masters.

Currently i have a minimum of 7 avalon masters eqach accessing the sdram.

now it is abvious that the sdram is the bottle neck.

4 of the custom avalon masters needs to read or write 32bit from or to the sdram each 160 clocks. but the avalon switch fabric assert a waitrequest for a read of up to 60 clocks cycles. so 4 of these avalon masters could lead to an access problem.

has anybody a recomendation of a different sdram controller ?

out of my head i think i remember that the sdram controller that is part of the sopc builder was called "poor" and that there are better ones.

The Avalon switch fabric i capable of setting some arbitrations.

i gave my own sopc modules higher numbers (2) than the nios2 (1) or the ethernet mac.

Any recomendations how to speed up the sdram access ? FClock ist 64MHz. And Quartus seems to have problems with incrementing fclk and fitting.

Michael Schmitt

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Hi,

    Having some imilar issues, I did some tests on the SDRAM controller.

    Yes there are better controllers, but the bottleneck is most of the time the clock domain crossing :

    -> running the SDRAM controller on 160Mc (better usage of the memory bandwidth) and the processor on 50Mc gives a slower system due to clock synchronisation.

    -> maybe a solution like the SDRAM controller from Microtronix can give you some speed advantages : 2 slaves on one controller, so if both the cpu and the other masters are working on a slower speed, the SDRAM controller can keep up due to its higher bandwidth on a higher clock speed. But here also, the clock synchronisation must been done.
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Thanks for your comments about this topic.

    I did also thought about running the sdram at a higher clock speed than the nios.

    The sdram used is a micron type and should run up to 133MHz.

    My external clock is 48MHz so i could tune the SDRAM up to 128MHz (8:3setting) and the nios with all other modules runs at 64MHz. This means the sdram has twice the speed than the nios, but taking into account that i get 6 clock penalty from the clock crossing domain the nios would run at 1/3 the speed it runs now.

    well i am not shure if 1/3 of nios execution speed is the problem if i could get the other masters to access the sdram within the max available clocks each masters for its access.

    but if i tune sdram to twice the speed of all other modules does this mean that i get the clock penalty of 6 clocks for each master ? does this slow down the whole stuff instead of speeding it up ?

    Michael Schmitt
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    I suppose if you get the other masters running at the same speed of the SDRAM, no extra clocks are needed for these transfers.

    I have some difficulties with generating systems with multiple clock domains, I don't know if the SOPC builder is alreday very stable on this issue.
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    just to understand you right ...

    if i tune all other masters to the speed of the sdram then there will be no performance loss. yes but that would lead to a big problem as currently 64MHz is the max quartus will fit. an ep2c50 will need 2-3 hours on a 3.8GHz P4 to fit without timing warnings.

    i had tried to setup a project with different clocks by just enabling the pll inside sopc to create 2 clocks and assigned them.

    nios, sdram jtag and epc at the fast one, all other at the slow one.

    did not succeded as nios still was unable to run properly even the flash prommer did not read out the correct sysid .. no matter if i connected sysid to the nios or the slow clock.

    i never had a nios running with different clock domains ... but no more actions on that currently
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Just the same issue here, trying to get the other masters to keep up to the speed of the SDRAM, just to prevent the penalty (or the problems) with the clock domain crossing.

    That is the reason why I want to try the Microtronix SDRAM controller, but some adjustments must been made by them (I'm waiting....). I have a lot of confidence in this controller, because it should have two independed slaves, that access the same memory. So I hope to connect my NIOS to one slave, my other (slower masters) to the other. And because the SDRAM controller itself runs at a faster speed, it should be possible to serve both interfaces.

    Of course there is the same penalty then for the clock domain crossing, but I plan to use an asynchronuous RAM to store the fast part of the program/data.

    I let you know when I have tried.

    Stefaan
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Hi everyone!

    I had the same problems with the sdram controller. And as the result I wrote my own controller which runs at 125 Mhz on Ep1C12 with speed grade 8.

    I tested it with nios core at 75 Mhz + video generation unit as an 8 words burst read master.

    Video unit runs at two clocks - 24Mhz and avalon interface block works at the same speed as sdram. So you can see that all synchronisations of clk were done inside my component, not with avalon bus. Furthermore this double master system works perfectly.

    Still the core needs testing, therefore I send it to MSchmitt and I hope to post it at opencores.org soon.

    It would be great if you join me.

    PS. Remember it's just the begining of the project and I haven't written any documentation, just basic comments inside source code.

    Good luck!
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Sounds interesting,

    if you need someone to beta test, I can try if I have some spare time. Just let me know.
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by ntpqa@Sep 6 2006, 11:12 AM

    hi everyone!

    i had the same problems with the sdram controller. and as the result i wrote my own controller which runs at 125 mhz on ep1c12 with speed grade 8.

    i tested it with nios core at 75 mhz + video generation unit as an 8 words burst read master.

    video unit runs at two clocks - 24mhz and avalon interface block works at the same speed as sdram. so you can see that all synchronisations of clk were done inside my component, not with avalon bus. furthermore this double master system works perfectly.

    still the core needs testing, therefore i send it to mschmitt and i hope to post it at opencores.org soon.

    it would be great if you join me.

    ps. remember it's just the begining of the project and i haven't written any documentation, just basic comments inside source code.

    good luck!

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18111)

    --- quote end ---

    --- Quote End ---

    Hi NTPQA,

    what about your SDRAM Core?

    I&#39;m very interested in that. Could i get the Core for testing?

    Thanx

    Marco
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by mschmitt@Sep 1 2006, 07:20 AM

    maybe somebody has a recomendation for me ...

    i use the sdram controller that is part of the sopc builder.

    the external sdram is 2 chips each 16 bit wide.

    inside the fpga cycloneii there are several avalon masters.

    niosii, 100mbit ethernet mac and some custom avalon masters.

    currently i have a minimum of 7 avalon masters eqach accessing the sdram.

    now it is abvious that the sdram is the bottle neck.

    4 of the custom avalon masters needs to read or write 32bit from or to the sdram each 160 clocks. but the avalon switch fabric assert a waitrequest for a read of up to 60 clocks cycles. so 4 of these avalon masters could lead to an access problem.

    has anybody a recomendation of a different sdram controller ?

    out of my head i think i remember that the sdram controller that is part of the sopc builder was called "poor" and that there are better ones.

    the avalon switch fabric i capable of setting some arbitrations.

    i gave my own sopc modules higher numbers (2) than the nios2 (1) or the ethernet mac.

    any recomendations how to speed up the sdram access ? fclock ist 64mhz. and quartus seems to have problems with incrementing fclk and fitting.

    michael schmitt

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18013)

    --- quote end ---

    --- Quote End ---

    You say "I use the sdram controller that is part of the sopc builder". Are you talking about the SDRAM v3.4.0 DDR/DDR2 Altera SDRAM Megacore IP ?

    BR
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by bigboss25@Sep 17 2006, 10:03 AM

    you say "i use the sdram controller that is part of the sopc builder". are you talking about the sdram v3.4.0 ddr/ddr2 altera sdram megacore ip ?

    --- Quote End ---

    No.

    I mean the SDRAM controller and not the DDR/DDR2 IP.

    Out of my head the current version is V6.01

    Michael